hey guys homework help

If I understood correctly what you want to obtain, your code is a mess.

In particular: Why that 9bit register for a single output?

You can do it with this much simpler code, involving a simple shift register.

module part1a(clk, in, reset, out);
input clk, in, reset;
output out;
reg  out;
reg  shifter;
always @(posedge clk or posedge reset)
begin
 if (reset)
   begin
      out <= 1'b0;
      shifter <= 4'b0101;
   end
 else
   begin
      if (shifter == 4'b0000)
             out <= 1'b0;
      else if (shifter == 4'b1111)
             out <= 1'b1;
      shifter <= { shifter , in };
   end
end

This is only sort of template; check syntax and operation.

Regards