Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHelp! Simulation Vector Output Issue
Gurus for this forum, I'm a student doing an ASICS and FPGA module at college in the UK and one of my tasks is to build a device using the drag and drop method, no vhdl allowed :( and if im ho...
Altera_Forum
Honored Contributor
16 years agoMade a new project and copied the file, renamed it and its now working fine.
WTF Thanks anyway guys