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Altera_Forum
Honored Contributor
Honored ContributorHelp! Simulation Vector Output Issue
Gurus for this forum, I'm a student doing an ASICS and FPGA module at college in the UK and one of my tasks is to build a device using the drag and drop method, no vhdl allowed :( and if im ho...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Could this be a design error? --- Quote End --- It sounds like.
