Altera_ForumHonored Contributor15 years agoHelp required with the FreqSweep example I am trying to understand the working of simulink models on FPGA. I am following the HIL design example that is illustrated in the DSP builder handbook volume 2 (pg. 5-3) I followed the whole proc...Show More
Altera_ForumHonored Contributor15 years agoYes. They both point to 10.0. The same error appears. Please help..
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