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Altera_Forum
Honored Contributor
15 years agoHelp - trying to combine a state-machine file with a bdf schematic
Hi, first time posting. I am new to Q II and FPGAs and am trying hard to learn but am handicapped in that I have very little VHDL experience and no courses under my belt, just self instruction (and I...
Altera_Forum
Honored Contributor
15 years agoAfter searching more dilegently I think the solution in my case is to use a bsf so it appears I am once again past a small hurdle without delving into the VHDL. Learning is fun if you don't mind the pain.
The SM wizard generates the VHDL which in turn generates a block symbol for connection in a bdf. Jack