Help - trying to combine a state-machine file with a bdf schematic

Thanks, your reply gives me information as to the general nature of the challenge. However, I am very handicapped relative to VHDL. Specifically, I have not done any programming, only reading (quite a lot) trying to understand a little about the subject. Initially Q II (using V9.0) was very challenging so I decided to try out schematic capture and familiarize myself with the megafunctions and this was not a bad idea because Q II itself is no longer a problem (one small hurdle).

I have recently muddled my way through the graphical SM tool and was pleased with that. Of course having done such a SM it was quite obvious that I was really working with a VHDL file and that makes sense. So the question became the one I submitted - how can I create a bdf schematic that utilizes the SM. As you now can more fully appreciate I was hoping at this point to avoid detailed VHDL involvement and just work with graphical tools because the VHDL is not easy to get up to speed on (I have little programming experience in my background and am now retirement age). At least I'm not a university student trying to get others to answer my assignment but I still feel embarrassed (:>)).

I know that ultimately an HDL is the only way to go for a younger engineer hoping to be useful as an FPGA programmer but I wanted to have some fun learning and using the DE-2 kit without the challenge of fully teaching myself VHDL.

So is there any hope for me in my present circumstance? Help in Q II is not much help unless one already has a pretty fair idea what's going on.

Thanks for taking the time to give me the initial direction. I recognize the key lies in instantiating another file so that there can be interaction but like I said even that is presently a challenge because of my lack of VHDL experience. I guess this can't be tackled graphically??

Jack