Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHelp - trying to combine a state-machine file with a bdf schematic
Hi, first time posting. I am new to Q II and FPGAs and am trying hard to learn but am handicapped in that I have very little VHDL experience and no courses under my belt, just self instruction (and I...
Altera_Forum
Honored Contributor
15 years agoYou can use the "create HDL from current file" in order to obtain a VHDL or Verilog file that can be added to your project and instantiated in the top level entity.
Otherwise, if you prefer schematic, you can "create symbol" from current file. This creates a symbol that you can instantiate in a top level bdf file. I've no clue on how to handle the active low/high levels of the pushbuttons in the automatically created state machine.