Greetings, How can I perform pass-through fitting (place and route)

In FPGA architecture, there is no tristate primitive component in the core, specifically in LE block. Look at Cyclone II LE structure https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc2/cyc2_cii5v1.pdf, Figure 2-3 Tristate only exists at the input or output port. So this is why your "tristate inverter" is translated to a mux. It is not possible to implement such design in FPGA.