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Altera_Forum
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15 years ago

Finite state machine problem

Hi, I have a state machine with 32 states. Assume the states transitions are sequential following the state number (ie it start at state 32 and followed by state 1 and followed by state 2 ..)...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Is the project schematic capture or HDL VHDL Verilog?