Forum Discussion

bruceylee's avatar
bruceylee
Icon for New Contributor rankNew Contributor
3 years ago

error budget model for the measurement system with MAX 10 FPGA Device

hello, intel tech support: i will appreciate if you share with me an example of error budget ( such as output voltage) due to 1) Gain Error due to Resistance Tolerance 2) Internal Offset V...
NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Per my checking, we follow JEDEC guidelines on process technology and reliability qualification methods.


All our process and product development efforts, including performance and reliability evaluations, have some form of error budgets. However, we don’t share this information as only the final product matters to customer. The final product conforms to JEDEC guidelines.


Hope this clarify.


Regards,

Aiman