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Altera_Forum
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15 years ago

DE2 Lab 7, Part 7 (VHDL) - Digital Logic

I just started learning VHDL and FPGA programing a couple of weeks ago and am currently working on Lab 7, Part 7 of the DE2 digital logic VHDL labs provided by Altera. In this lab you have to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Dont use the keys as clocks.

You're asking for trouble.

Clock the process with the system clock. You can make a falling edge detector by registering the key states, then you can do:

if key(0) = '0' and key_old(0) = '1' then

Clocking the process will also get you away from the incomplete sensitivity list you have at the moment.

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Thanks a lot for the advice, exactly what I was looking for. I implemented your method and it works great. Thanks.