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Altera_Forum
Honored Contributor
Honored ContributorDE2 board VGA Dispaly
Hello All,
I am trying to use the board's SRAM to store an image and dispaly it on the screen. I designed a project using QuartusII and was able to manage the VGA dispaly timing. I used a reference design from John Loomis Webpage. http://www.johnloomis.org/digitallab/vgalab/vgalab3/vgalab3.html which is very helpful and nice. However, I am having a problem in dowloading the raw image file to the SRAM. My question is: How can I get a typical 640 X 480 bitmap image to be stored in the SRAM? I tried to use Terasic ImgConv, but it doesn't work :( I appricate your help. Thanks42 Replies
Altera_ForumAre you using Nios in this ref. design? If you are using it then you can download your raw data file of image (converted from BMP) to the on-board flash and then when NIOS program gets executed it copies your image from flash to sram!
If you are not using Nios then it would be tough to load image directly. I think terasic provides software which can load image to SRAM using custom-JTAG interface.- Altera_Forum
it's easy
may be you didn't check the "file length"？ - Altera_Forum
Hi monish
You don't explain, if you want o show a RGB image in the VGA.... I tried the same as you, but I began showing a 320x240 8bit grayscale, with my own code in the FPGA. Also, I did a RS232 comunication to pass the data from my PC to the DE2 board, and a simple software in my PC to extract the bmp header from the file to send, and send all usefull bytes of the bmp file to DE2. It's quiet easy. (Avoiding the DE2 control panel use) Then I did the same, but in 320x240 pixeles in RGB, obviously I use the DE2 on board SRAM to store the image data in both cases, all was succesufully. And all this for like a "learn practique". To show a 640x480 pixeles in RGB mode on VGA, SRAM is out of space, so I decided to use SDRAM to store the data, I'm trying this now...but I still can't get manage the SDRAM data as fast as I need. If you want, or ask some about the FPGA code...I can post it (But I'm so begginer like you...so maybe my code is not very "academic") - Altera_Forum
cómo lo hiciste?
puedes mandarme tu código para verlo? también necesito desplegar una imagen para hacer detección de bordes sobel. ************ how did you do it? can you please send me your code to watch it? I need to display an image to do an edge sobel detection. - Altera_Forum
Hi.
Here´s some code to try the 320x240 image. Let me know if it was usefull. - Altera_Forum
Bad luck, my fpga (FLEX10k) does not support the atlpll megafunction.
But thank you any way. - Altera_Forum
You can replace the VGA_CTRL_CLK, and the Play_Clock, with two hardware clocks, then avoid the altpll.
- Altera_Forum
Ups, I'm a beginner on FPGA programming, verilog, vhdl and all those languages.
I really wouldn't know how to do that. Could you help me out? Thanx - Altera_Forum
Hi.
Hardware clocks mean that you could have two oscillators with the same frequency as the PLL outs, connect it to some external pins of your demo board, and assign in the verilog code that pins as input for clocks. You only need at least a minimal knowledge for that. Like I´m a beginner too, will be not so difficult to understand my code. and where to modify it. PD: En Inglés es: "Oops" :) Suerte !! - Altera_Forum
Ok, I'll try it.
Sorry about the ups and the oops, i got my english and my spanish mixed up. Gracias!
