Hello,
I recently got a migration that works despite having a small error in the order in which the 7 segments are displayed.
The biggest problem I found was finding out that Qsys alters certain lines of code, but reviewing a bit in this forum and with the help of altera wiki I made the following changes:
these names were modified in the qsys generated file:
pll_c0_system -> pll_c0_out
pll_c1_memory -> pll_c1_out
pll_c2_audio -> pll_c2_out
Once renamed to its original form make the changes mentioned in:
http://www.alterawiki.com/wiki/new_qsys_issues#wrong_vhdl_example_in_qsys_for_different_blocks With these changes the rest was only to review and add to the project of quartus the file alt_pll.qip of the original project.
At this time the project performs the functions of sending and receiving packages but I am not happy with that error of the 7 segments.
I leave the project link. I will keep you informed as I progress.
http://ge.tt/24w3vfp2 Best Regrads.