Honored Contributor
Honored ContributorI did read user guide for the HSMC_ADA which is what confused me a lot.
I read this document and the ADC spec sheet and I can't tell what type of interface between the DE2-115 and the HSMC_ADA other than the fact that it is HSMC. There are 14 output ports for the HSMC_ADA for each ADC and DAC inputs/outputs. So I assume that each port is running in parallel 1-bit at a time at 65 MHz for the ADCs and the DACs ports run in parallel 1 bit for each port at 125 MHz. However, what confuses me is that in the FPGA data sheet of the Cyclone IV, there are different types of I/Os that run at specific speeds of all which I have no idea how to interpret. All I know is I want to be able to receive 14-bits at 65 MHz which equals to 910 Mbps, and transmit at 1750 Mbps. How do I know what type of I/Os my board is going to be using so that I can understand based on the data sheet if the HSMC_ADA will receive/transmit @ full speed with my FPGA? PS Dave, I have seen an old post of yours where another student is inquiring about whether the DE2-115 trying to receive 14-bits at 65 MSPS via LVDS. .alteraforum.com/forum/showthread.php?t=28711 Clearly he could not receive 14-bits @ 65 MSPS via LVDS, but my situation is different in the sense that I do not know if I am receiving in LVDS or not. This is what worries me because I don't exactly know how to interpret the FPGA IOs speeds and what type the HSMC_ADA uses (I am a student trying to learn these things). I'm trying to prevent myself from buying two boards that I have no idea if they will work in full capacity together.
