My apologisies to Terasic and people interested:
once i have lowered clock within access time of sram on the board everything was fine. Still can not explain why original Terasic design did not work.
---below my original answer: ----
I am pretty sure that original IP from terasic “Terasic_sram “ has some problem. I had simple test writing and reading values from SRAM and it failed. Then I took one of the original sample design from de2-115 and tried to make simple “hello world”. It did load when code was in on chip or sdram. It did not load when i asked to download code to sram. In addition to this I have tried to run the same sram test (code in sdram) and it failed. My simple memory tests works nicely on all other boards.
Zbigniew , sydney