DE1-SoC Computer with Nios V design files

Hi Vincent,

Apologies for the delay as currently having issues backlog on my end. As for the request, unfortunately we do not store any Terasic design files with us, did a search through our database (Altera) and I don't see anything available for DE1 SoC. It looks like it is stored at a separate location as this is part of university program collaboration between Intel/Altera and Terasic, perhaps on fpga academy github (https://github.com/fpgacademy)

Probably you could try email them to see whether they have the latest NiosV Quartus project (fpgacademy.org@gmail.com)

Alternatively I saw in the document source code are bundled as part of Monitor Program (https://fpgacademy.org/tools.html)

However Monitor Program only have the older NiosII designs in there, but worth a try if you just need the qsys (it includes the Quartus project as well)

Other areas I found from those documents in fpgaacademy

https://github.com/fpgacademy/Design_Examples/releases/tag/v1.0

or you can get from the ghrd example from Terasic website that has the qsys as well (under DE1-SoC CD-ROM , depends on your hardware revision)

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=836&PartNo=4#contents

Thanks

Regards

Kian

Hi Vincent,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thanks

Regards

Kian