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Altera_Forum
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15 years ago

DE0: Nios 2 with custom logic and PIO.

Hi, I'm just getting started with the DE0-board. (Cyclone III). My goal is to have a Nios 2 soft core processor together with UART. I also want the Nios processor to act master on the avalon bus c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The timestamp mismatch means that the SOPC project that is configured inside the FPGA isn't the same than the one your software was compiled for. Be sure to accomplish the following tasks, in that order:

  • Generate the system from SOPC builder, save and quit SOPC builder

  • Compile the design in Quartus

  • Program the FPGA with the compiled project

  • Compile your system library (old IDE) or regenerate your BSP (new IDE)

  • Compile your software

  • Download your software

With the old IDE the system library is automatically rebuilt when there is a change in the SOPC project each time you 'make' your application, but it seems that with the new one you need to regenerate the BSP manually.