Forum Discussion
Altera_Forum
Honored Contributor
14 years agoFirst of all "Don't say sorry"
Now i think you dont need think about the verilog file because i have provided and it will work so dont worry In left pane of quartus project navigator window,click on "files" tab and right click on your required verilog file ( for eg.it is f_divider.v),you will see "create symbol files for the current file".click on that. Now you made block symbol from your verilog file. Hope this will help you little and don't say sorry again.No body is perfect :)