custom ip core

hello anand,

I have made some change as follows:

• in Platform Designer: in my IP ("myrossler"), I have added an avalon memory mapped slave with (avalon_slave_read[1],)avalon_slave_readdata[8],avalon_slave_write[1],avalon_slave_writedata[8]),
• In quartus: in DE2_115_computer.vhd, in component and port map added my_rossler_conduit_end_read1 : ou std_logic_vector (31 downto 0); for read1,read2 and read3, then I connected them with myrossler_read1, myrossler_read2 and myrossler_read3, then I compiled.

My problem is: 12002 Port "avalon_slave_read" does not exist in macrofunction "myrossler_0"

12002 Port "avalon_slave_readdata" does not exist in macrofunction "myrossler_0"

12002 Port "avalon_slave_write" does not exist in macrofunction "myrossler_0"

12002 Port "avalon_slave_writedata" does not exist in macrofunction "myrossler_0".

just to remind you "myrossler" is a custom IP that has inputs clk and rst and outputs 3 32 bits signals that I want to exploit

Thank you very much anand