Honored Contributor
Honored ContributorWithout going in to your code in detail I can offer the following advice.
http://www.asic-world.com/verilog/ Contains a lot of info on Verilog coding which may be of interest. The code fragment you posted is a bit out of context, the code following is important to. always@(posedge iCLK or negedge iRST_n) begin if (!iRST_n) begin rRed<=0; rGreen<=0; rBlue<=0; end else if ({mirror_sw,iY_Cont[0],iX_Cont[0]} == 3'b011) begin if (iY_Cont == 12'd1) begin rRed<=wData1_d1; Basically this means that the code following the always is executed on a rising edge of iClk (This is the clock) or a falling edge of iRst_n (This is a reset). The first if(iRST_n) is executed when when iRST_n = 0; The else part is executed when iClk is rising. This is the synchronous part of the process and controls the inputs to flip flops. These are just a few pointers and I really suggest that you read a good tutorial on Verilog programming. Good luck
