Controller IP for DE10-Lite SDRAM

Hi Tim,

Please find my answer in points below.

"What do you mean by "need to use own design to interface with the SRAM devices"? I thought that the IP would be the interface to communicate with my SDRAM. What am I getting wrong here?"

• Yes the IP will create a module or design to interface with the memory device.
• But in this case, the MAX 10 device has it's own supported IP for memory devices and it's limited to memory protocol.
• So in this case, you need to create your own memory design or use some example designs available from the board vendor.

"By example design you mean the "SDRAM_RTL_Test" in the Demonstrations directory aren't you? That's a great idea.

To be honest I'm not very familiar with verilog, I only used VHDL yet so I was hoping for some VHDL boilerplate."

• Yes the example design from Demonstrations directory.
• Maybe you can use the converter to convert Verilog code to VHDL.

"Am I right that - if I would work in verilog - I could simply copy the "Sdram_Control" entity and use it as sdram controller in other projects? Do you know if I have to consider something before using it in my own design? (I would probably try to translate it to VHDL and use it then)."

• Yes I think you can copy the design into your design and make the connection similar to example design.
• The parameter should be matched with the SDRAM device already.

Regards,

Adzim