Clarification of documentation for HPS TIMER polling operation

Terasic designed the board and wrote the document, but the HPS timer is Intel FPGA IP. The Cyclone V user manual contains the same information, that the I bit masks the interrupt. It doesn't say it also prevents the status bit from coming on. apparently this unit is based on the Synopsys DW_apb_timer object, but documentation for that unit seems to require membership in Synopsys. Is there no functional description that can clarify what it actually does with the I bit?