New Contributor
Regular ContributorHello Arnie,
Both statements you mentioned above are possible. Here is the manual menu that you can refer to for this device: https://www.intel.com/content/dam/altera-www/global/en_US/portal/dsn/42/doc-us-dsnbk-42-4904342209-de1-usermanual.pdf
Thanks
New ContributorHello AminT,
I'm sorry if you didn't understand my post. I have the manual for the DE-1 board. We use them for our teaching. That isn't the issue at all. The issue is how to access the ARM bus inside the Cyclone V FPGA. After doing some research, I found a block diagram that shows why it probably isn't possible to do what I want to do. The reason is that there is a cache sitting between the ARM core and the FPGA fabric.
I can write to specific addresses and write through the cache, but that is only to specific addresses. I can't see the bus. Unless there is a way to turn off the cache and bring all bus signals through to the FPGA, I don't see how what I want to do would be possible.
Arnie
Regular ContributorHello Arnie,
1. I think you are referring to the block ‘FPGA to HPS’ at the bottom of the figure Cyclone V SoC Hard Processor System on this page: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v/features.html. The logic implemented in FPGA part can be read by the ARM core through the “FPGA-to-HPS: Configurable 32, 64, or 128 bit AMBA AXI interface”. You would also want to monitor the AXI bus by using Signal Tap.
2. You may have to duplicate the registers driving the AXI bus to the GPIO pins, so that they can be observed using external logic analyzer.
I hope this helps.
Thank you,
Amin
Regular ContributorHello,
This is additional document that you can refer to: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v4.pdf
Thank you,
Amin
