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skyviper
New Contributor
New ContributorBecome an FPGA Designer in 4 Hours SDRAM controller IP outdate
In the "Become an FPGA Designer in 4 Hours" course the ../demo/cores/sdram_ctrl/synthesis/sdram_ctrl.qip is out of data with Quartus prime 23.1std.1. I get entity errors when trying to use the IP upg...
FvM
Super Contributor
Super ContributorHi,
the posted archive doesn't contain meaningful SDRAM controller code just a dummy .v and .qip files without actual function.
Are you starting with an existing example design, if so what is it?
Are you using this design example Intel® MAX® 10 FPGA – Become an FPGA Designer in 4 Hours Lab
