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Altera_Forum
Honored Contributor
Honored Contributorbasic questions
Hi everyone, I'm having trouble with the code I posted below. I'm trying to design an ALU and am having conceptual problems. Seems like for the case when sel is "1000" I get errors saying ...
Altera_ForumHonored Contributor
Honored Contributor<= is for assigning a signal
:= is for assigning a variable. Signals and variables behave differently. Variables are assigned immediately whilst signals are assigned when a wait occurs or the process suspends. I highly recommend you dont use variables until you unstand the implications of their behaviour. There is nothing you need a variable for - you can do everything you need for synthesis with signals, and it wont give you odd behaviour. Std_logic_vectors are intended to just represent a collection of bits. Unsigned/signed types are meant to represent unsigned/signed numbers.
