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Altera_Forum's avatar
Altera_Forum
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10 years ago

Ask for help with Altera Monitor Program

​hello every body,

iam working on the tutorial: introduction to altera Qsys tool, and using the

Altera monitor program with DE0 to download the programm into the board, but

i obtain these errors after compile and load action:

Possible causes for the SREC verification failure:

1. Not enough memory in your Nios II system to contain the SREC file.

2. The locations in your SREC file do not correspond to a memory device.

3. You may need a properly configured PLL to access the SDRAM or Flash

memory.

So can any one help me please

thax

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    DE0-Nano, DE0-Nano-SoC, or just DE0?

    In Qsys, how large did you make your on-chip-memory (I believe default is 4096 bytes)?

    Did you use the simple program given in the tutorial, or a more complex one? If you did

    not change the defaults, you will have a small amount of memory to load your program, and it may not fit in memory (Item 1 in the list).

    Did you ensure that the base address of your on chip memory is 0x00? If did not lock the on-chip memory to that base address (In Qsys) and then

    selected assign base addresses, the base for the on-chip memory will likely not be 0x00.