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Altera_Forum's avatar
Altera_Forum
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12 years ago

Altera_UP_Clocks IP core

Hi all,

i am beginner in coding RTL. I want to use the Altera_UP_Clocks component in order to use SDRAM on my DE2-115 board. In the component library i can not find Altera University program category. I have set up quartus 12.0, 12.1, 12.1sp1 respectively. But no luck, it seems i am missing something.

I downloaded Altera_UP_Clocks core from a website, but i can not figure out how to integrate verilog files into Qsys.

Actually it should be included in quartus that Altera university program offers. Could you please guide me ?

Thanks a lot.

Cem

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    In addition to this, i managed to run the script called install_altera_upds in my linux machine. It seems it created 'ip' directory including IP cores in quartus directory.

    /altera/12.1/quartus/ip/University_Program/

    In this directory 'ls' command gives me:

    altera_up_avalon_clocks

    Audio_Video

    Communications

    license.txt

    altera_up_clocks

    Bridges

    Input_Output

    Memory

    But i am not able to see these IP core in Qsys as component ? There is no University_Program and related files. How to make them appear in Qsys ? Any help is greatly appreciated !!!