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Honored Contributor

9 years ago

Altera Monitor Program resetting and pausing target processor: FAILED

I have a design for a simple NIOS II processor on the DE1-SoC board that assigns the value on the switches to the LEDs (standard hello world) but this design integrates the SDRAM on the board into it...

Altera_Forum

Honored Contributor

9 years ago

Hi, I assume that the SDRAM will act somewhat like a frame buffer, and the RTL will just continuously read from there and output it (something like RAW2RGB ). If this is the case, take a look at Terasic's example for D5M:

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=68&no=281&partno=3

Perhaps you can modify the code from thence.

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Altera Monitor Program resetting and pausing target processor: FAILED

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