Altera Monitor Program resetting and pausing target processor: FAILED

I have tried restarting the Altera Monitor Program, and ensuring I use the quartus programmer to flash the device before I start the monitor program, this still gives the same problem. If I don't use the SDRAM controller in the qsys design and instead use on-board RAM or ROM for the reset and exception vectors then the system works. Which makes me suspicious of the SDRAM components. However if I use some test code that uses an SDRAM controller and periphery (but with no NIOS) then that program works ... so i suspect the SDRAM isn't broken...

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I have also revisited all of the settings for the SDRAM controller to make sure they match those in the tutorial and even tried both the NIOS II Classic and the NIOS II 2nd Gen cores however I still get the same error.

Incidentally I'm not actually looking at using the SDRAM with a NIOS II controller, instead I would like to be able to have an interface where I can just write a value to a location in the SDRAM and then have a VGA controller reading the contents of the SDRAM and displaying on a screen, so if anyone has any more specific tutorials/information/reference designs for this then that would be most useful!