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Altera_Forum
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9 years ago

Altera Monitor Program resetting and pausing target processor: FAILED

I have a design for a simple NIOS II processor on the DE1-SoC board that assigns the value on the switches to the LEDs (standard hello world) but this design integrates the SDRAM on the board into it...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I've seen that message when I had a bad configuration file, or when I forgot to load the FPGA configuration before starting the monitoring program. You can narrow it down by seeing if the board works with a known good configuration file.