Forum Discussion
Occasional ContributorAktera ModelSim Lite GateLevel Simulation isn't timing accurate.
Could you try below flow:
In the Quartus tool, go to : Assignment -> Settings -> EDA Tools Simulation -> Simulation -> More EDA Netlist Writer Settings -> generate functional simulation netlist -> turn it to off.
Then try to compile again to see if the .sdo file generated.
As you may notice in the netlist setting, there is note saying : If the device does not support timing simulation, then only the functional-simulation netlist is available.
Fyi, Timing simulation is not supported for Arria V, Cyclone V, Stratix V, and newer families. If your device does not support timing simulation, use Timing Analyzer static timing analysis rather than gate-level timing simulation.
Occasional ContributorThank you, that 'generate functional simulation netlist' button is well hidden.
Yes, I'm annoyed about loosing both timing simulation and the fact that the newer families during timing analysis only reports 1 last worst path instead of a good 100 of them since that 1 single worst path may be due to the fitter working around more troublesome logic elsewhere in the design.
Super ContributorYou may checkout "Generate Timing Report" in the Timing Analyzer User Guide on how to customize specific timing report.
If you have no further question, I will transition this thread to community support. And if you have a new question, feel free to open a new thread to get the support from Intel experts.
