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BrianHG's avatar
BrianHG
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Aktera ModelSim Lite GateLevel Simulation isn't timing accurate.

Hello, (I'm using QuartusPrime 20.1) I've made a simple project written in systemverilog, with a test bench file, which I compile and then do a GateLevel Simulation. The simulation works fine, ...
  • RichardT_altera's avatar
    RichardT_altera
    5 years ago

    Could you try below flow:

    In the Quartus tool, go to : Assignment -> Settings -> EDA Tools Simulation -> Simulation -> More EDA Netlist Writer Settings -> generate functional simulation netlist -> turn it to off.

    Then try to compile again to see if the .sdo file generated.

    As you may notice in the netlist setting, there is note saying : If the device does not support timing simulation, then only the functional-simulation netlist is available.

    Fyi, Timing simulation is not supported for Arria V, Cyclone V, Stratix V, and newer families. If your device does not support timing simulation, use Timing Analyzer static timing analysis rather than gate-level timing simulation.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

Could you try below flow:

In the Quartus tool, go to : Assignment -> Settings -> EDA Tools Simulation -> Simulation -> More EDA Netlist Writer Settings -> generate functional simulation netlist -> turn it to off.

Then try to compile again to see if the .sdo file generated.

As you may notice in the netlist setting, there is note saying : If the device does not support timing simulation, then only the functional-simulation netlist is available.

Fyi, Timing simulation is not supported for Arria V, Cyclone V, Stratix V, and newer families. If your device does not support timing simulation, use Timing Analyzer static timing analysis rather than gate-level timing simulation.

BrianHG's avatar
BrianHG
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Thank you, that 'generate functional simulation netlist' button is well hidden.
Yes, I'm annoyed about loosing both timing simulation and the fact that the newer families during timing analysis only reports 1 last worst path instead of a good 100 of them since that 1 single worst path may be due to the fitter working around more troublesome logic elsewhere in the design.