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The module Reset_Delay.v in DE2_D5M is generating 3 reset signals. They are separted in time. This is to allow different parts of the DE2_D5M system to be reset one after another.
The delay times for the reset are only arbitrary times in order to allow different modules / external peripherals to be reset in sequence. The time is however still below 1 sec.
Hope this helps.
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what i would like to know is why they use 1FFFF,2FFFFF and 3FFFF with a clock 50 MHz, i think that this are for the following time 42ms,63ms and 84 ms i have tried to calculate this time for a bust write in SDRAM, but don't have succes.
How are caculated this time ?
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