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Altera_Forum's avatar
Altera_Forum
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17 years ago

about the Reset_Delay.v in DE2_D5M

The following is excerpted from Reset_Delay.v of the project de2-d5m always@(posedge iCLK or negedge iRST) begin if(!iRST) begin ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The module Reset_Delay.v in DE2_D5M is generating 3 reset signals. They are separted in time. This is to allow different parts of the DE2_D5M system to be reset one after another.

The delay times for the reset are only arbitrary times in order to allow different modules / external peripherals to be reset in sequence. The time is however still below 1 sec.

Hope this helps.