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Altera_Forum
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11 years ago

a DE1-SOC + VIP (TPG+VCO) does synthesize but does not simulate

Hi ! I've been designing a very simple design. This is a test, inspired from Terasic's video demo to see how the clock and reset networks are set. This is a TPG connected to the video out c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi Pierre,

I'm glad to hear you got your design working. Thanks for posting feedback on how you solved your issue. Hopefully it'll help the next person :)

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Many thanks to you and to all the contributors of these very helping threads

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You're welcome.

Cheers,

Dave