a DE1-SOC + VIP (TPG+VCO) does synthesize but does not simulate

Hi Dave,

You are absolutely right.

I appreciate very much Altera's tools that allowed me to do in 2 weeks what I have

been unable to do with Xilinx for months. I started "from scratch".

So I have now a very positive attitude for Altera.

I also recommended to my colleagues (Université de Bretagne Sud, UBS, France) to switch

from Xilinx to Altera for their future designs.

Considering the problem I experienced, I must now admit that all works fine with 14.1

I probably made something wrong (but what ?) within the 1rst design.

The main difference is that I was using the "version II" of the TPG and the VCO, rather

than the original ones.

I confirm that, with all versions of these IPS, logical & physical synthesis ALWAYS WORKED.

Only with version II, I had simulation troubles (compilation libraries).

But, I'm still a beginner with Altera and I must continue to learn more :-)

The "probability of mistakes" is today far more on my side than on Altera's.

So, what's next now ?

I'll keep an eye on reproducible problems, for sure. And I will forward relevant data (.qar)

to Altera when needed.

Many thanks to you and to all the contributors of these very helping threads,

Pierre