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Altera_Forum
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11 years ago

a DE1-SOC + VIP (TPG+VCO) does synthesize but does not simulate

Hi ! I've been designing a very simple design. This is a test, inspired from Terasic's video demo to see how the clock and reset networks are set. This is a TPG connected to the video out c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You are totally right, the Terasic's ref design has been build with a 13.1 version, and I'm using a 14.1 version ...

I'll try this tomorrow, to check.

If it does not work, I'll contact Altera.

Many thanks for your advices,

Pierre

PS: the .qsf contents are:

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13

set_global_assignment -name LAST_QUARTUS_VERSION 13.1