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Altera_Forum
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11 years ago

a DE1-SOC + VIP (TPG+VCO) does synthesize but does not simulate

Hi ! I've been designing a very simple design. This is a test, inspired from Terasic's video demo to see how the clock and reset networks are set. This is a TPG connected to the video out c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Of course I tried to create an empty lib alt_vip_common_pkg: the same error occurs

I also tried to remove the line 77 to see what will happen later: an other error occurs later

There is really some useful stuff in that lib :-))))

Pierre