a DE1-SOC + VIP (TPG+VCO) does synthesize but does not simulate

Thank you very much Dave.

Of course, I immediately had a look to all these files for simulation.

In the .do file, there was no explicit ref to any alt_vip_common_pkg library to add or file to compile.

The compilation error comes from a VHDL file named "alt_vip_cvo_core.sv"

at the line 77: it contains a "import alt_vip_common_pkg::*;"

The file alt_vip_common_pkg.sv does exists in the same directory than

the alt_vip_cvo_core.sv, but it is not included in the .do file for

compilation.

I added it manually and reran the compilation: it fails when compiling

alt_vip_common_pgk.sv because the file is crypted. By the way, this was the

opportunity for me to discover this.

So, I suppose that there should be somewhere a

precompiled version of all these Altera's proprietary (and crypted) files.

And I searched everywhere ... (but not in the whole doc yet).

Unfortunately, there are no "modelsim" (I mean *.qdb) files about any VIP

unit under the Quartus 14.1 installation directory.

I suppose these precompiled libs for Modelsim must be obtained

somewhere: probably Altera ...

I will ask Terasic (the DE1-Soc board makers) how they simulated there

VIP demo when debugging it. For sure they did it !

I'll keep the community informed when I have fresh news.

If you have any suggestions, do not hesitate. I think I am stuck ...

Kind regards,

Pierre