3 to 1 Multiplexer Codes

since I've learnt some simplified ways,am i going the right way with this?

does it represent 3 to 1 mux?

library ieee;

use ieee.std_logic_1164.all;

entity chiong2_1 is

port (s : in std_logic_vector(1 downto 0);

u : in std_logic_vector(1 downto 0);

v : in std_logic_vector(1 downto 0);

w : in std_logic_vector(1 downto 0);

red:out std_logic_vector(7 downto 0);

op : out std_logic_vector(1 downto 0));

end chiong2_1;

architecture behavior of chiong2_1 is

begin

red<= s & u & v & w;

op<= u when (s(0) ='0' and s(1) ='0') else

v when (s(0) ='1' and s(1)='0') else

w when (s(0) ='0' and s(1) ='1') else

w;

end behavior;