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Altera_Forum's avatar
Altera_Forum
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16 years ago

2 to 1 Multiplexer Codes

I am going to post my VHDL codes for a 2 to 1 Multiplexer,im not sure if im heading the right way or not but i would like to get some feedback on what im doing. As you can see. SW(8) is my s ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

What you are doing makes your code hard to read and difficult to understand. Theres also a very useful VHDL construct for muxes

why not separate it out so it reads alot easier:

port (

s : in std_logic;

x : in std_logic_vector(3 downto 0);

y : in std_logic_vector(3 downto 0);

op : out std_logic_vector(3 downto 0);

);

architecture....

begin

op <= x when s = '0' else y;

end.