128 bit Avalon read/write

Hi,

I actually put this assignment in the code as well

assign wr_en_add_1=cs & wr & addr;

assign rd_en_add_1=cs & rd & addr;

where cs,wr,rd,and addr are mapped to signal chipselect,write, read, and address of avalon in SOPC Builder.

The write block above is actually like this

always@(posedge clk)

begin

if (wr_en_add_1)

begin

if (index==0)begin fifo_in[31:0] <=wr_data; index=1;end //wr_data is to be //map with the write signal of avalon bus, which is the user input signal

else if (index==1)begin fifo_in[63:32] <=wr_data; index=2;end

else if (index==2)begin fifo_in[95:64] <=wr_data; index=3;end

else if (index==3)begin fifo_in[127:96] <=wr_data; index=4;end

end

After I check with the above code, it seem like the avalon only take the first wr_data from NIOS, an ignore the rest when I want wr_data to have another value to assign to other fifo_in i.e my customer logic only receive fifo_in[31:0] !

Do you have any idea ?

Thanks