128 bit Avalon read/write

Hi, let me clarify a bit of my problem

In the interface module, I created an array of 128 bit and divided this into 4 range of 32 bit each. For every posedge clk signal, each 32 bit chunk will get an input. Something like this:

//========================================

always@(posedge clk)

if (index==0)begin fifo_in[31:0] <=wr_data; index=1;end //wr_data is to be //map with the write signal of avalon bus, which is the user input signal

else if (index==1)begin fifo_in[63:32] <=wr_data; index=2;end

else if (index==2)begin fifo_in[95:64] <=wr_data; index=3;end

else if (index==3)begin fifo_in[127:96] <=wr_data; index=4;end

On the other side, I wrote similar code for reading the result from the output of my custom logic, which is also 128 bit.

My custom logic only need the chunk of data of128 bit to process and that is it, dont have to get another one.

To run the test using NIOS, I create 4 32-bit data and use IOWR, then IORD to the base address 1 to get the result:

a=0x00006464;

b=0x00006464;

c=0x00000000;

d=0x00000000;

IOWR(ADD_INTERFACE_0_BASE,1,a);

IOWR(ADD_INTERFACE_0_BASE,1,b);

IOWR(ADD_INTERFACE_0_BASE,1,c);

IOWR(ADD_INTERFACE_0_BASE,1,d);

j=IORD(ADD_INTERFACE_0_BASE,1);

k=IORD(ADD_INTERFACE_0_BASE,1);

l=IORD(ADD_INTERFACE_0_BASE,1);

m=IORD(ADD_INTERFACE_0_BASE,1);

It turn out that either write or read or both dont work.

My question is:

1. Is this problem come from the synchronize of the clk cycle between the custom logic and avalon bus (or something else) that the fifo_in never actually get enough chunk of data provided ? How to fix this ?

2. On the read part, what is a good way to read from a 128 bit fifo_out through the avalon bus like above

I have been with this in for a few days already and still get stuck. I would really aprreciate if anyone can help me out

regards