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Frequent Contributor[Test only]Cyclone V emmc speed
Cyclone V emmc speed
Hi,
For Cyclone V I have 2 questions as below
1) Use eMMC ( v4.5 HS-200) but read/write throughput only Write 25MB / Read 45M /s . What's the limitation ?
2) What eMMC spec (e.g: eMMC v4.1 ) that Cyclone V SoC can support ? And how's the max throughput ?
Thanks
1. Limitations with eMMC v4.5 HS-200
Your eMMC v4.5 chip supports the HS200 standard (which utilizes a 200 MHz clock to achieve up to 200 MB/s), but the Cyclone V controller physically cannot operate at those speeds due to three hard limitations:
Maximum Clock Speed: The controller's interface output clock (SDMMC_CLK_OUT) caps out at 50 MHz in high-speed mode (a minimum clock period of 20 ns).
Single Data Rate (SDR) Only: The SD/MMC controller only supports SDR mode. It lacks hardware support for Dual Data Rate (DDR) transfers, meaning it can only transfer data on one edge of the clock cycle.
Controller Standard: The HPS SD/MMC controller is based on the Synopsys DesignWare Mobile Storage Host, which was designed before the HS200 mode existed. It does not have the hardware circuitry to support JEDEC eMMC v4.5 or v5.0 high-speed modes.
Because of these factors, your eMMC v4.5 chip is automatically falling back to legacy backward-compatibility modes to communicate with the Cyclone V. The speeds you are currently getting (45 MB/s Read, 25 MB/s Write) mean your system is actually optimally tuned — you are successfully hitting the practical ceiling of the silicon's capabilities.
2. Supported eMMC Specs and Maximum Throughput
Supported Specification: The Cyclone V SoC officially supports up to eMMC version 4.41. Newer eMMC chips (like your v4.5 or v5.0 modules) are widely used and supported, but they will operate strictly within 4.41 constraints.
Bus Width: The controller supports 1-bit, 4-bit, and 8-bit data widths.
Theoretical Maximum Throughput: 50 MB/s. This is calculated using the absolute maximums of the controller: a 50 MHz clock speed multiplied by 1 byte per clock cycle (using an 8-bit bus in SDR mode).
Practical Maximum Throughput: Factoring in normal protocol overhead and filesystem operations (like ext4), real-world read speeds typically max out right around 40 to 45 MB/s. Write speeds are inherently slower due to the flash memory's page erase cycles and wear-leveling algorithms, making 20 to 25 MB/s the expected maximum.
2 Replies
KianHinT_altera1. Limitations with eMMC v4.5 HS-200
Your eMMC v4.5 chip supports the HS200 standard (which utilizes a 200 MHz clock to achieve up to 200 MB/s), but the Cyclone V controller physically cannot operate at those speeds due to three hard limitations:
Maximum Clock Speed: The controller's interface output clock (SDMMC_CLK_OUT) caps out at 50 MHz in high-speed mode (a minimum clock period of 20 ns).
Single Data Rate (SDR) Only: The SD/MMC controller only supports SDR mode. It lacks hardware support for Dual Data Rate (DDR) transfers, meaning it can only transfer data on one edge of the clock cycle.
Controller Standard: The HPS SD/MMC controller is based on the Synopsys DesignWare Mobile Storage Host, which was designed before the HS200 mode existed. It does not have the hardware circuitry to support JEDEC eMMC v4.5 or v5.0 high-speed modes.
Because of these factors, your eMMC v4.5 chip is automatically falling back to legacy backward-compatibility modes to communicate with the Cyclone V. The speeds you are currently getting (45 MB/s Read, 25 MB/s Write) mean your system is actually optimally tuned — you are successfully hitting the practical ceiling of the silicon's capabilities.
2. Supported eMMC Specs and Maximum Throughput
Supported Specification: The Cyclone V SoC officially supports up to eMMC version 4.41. Newer eMMC chips (like your v4.5 or v5.0 modules) are widely used and supported, but they will operate strictly within 4.41 constraints.
Bus Width: The controller supports 1-bit, 4-bit, and 8-bit data widths.
Theoretical Maximum Throughput: 50 MB/s. This is calculated using the absolute maximums of the controller: a 50 MHz clock speed multiplied by 1 byte per clock cycle (using an 8-bit bus in SDR mode).
Practical Maximum Throughput: Factoring in normal protocol overhead and filesystem operations (like ext4), real-world read speeds typically max out right around 40 to 45 MB/s. Write speeds are inherently slower due to the flash memory's page erase cycles and wear-leveling algorithms, making 20 to 25 MB/s the expected maximum.
- BoonBengT_Altera
Moderator
Please find the below suggested answer:
eMMC Version Support
The Cyclone V HPS SD/MMC controller supports eMMC with 1-bit, 4-bit, and 8-bit data bus widths, per MMC version 4.41. So your statement that v4.5/v5.0 chips fall back to v4.41 constraints is correct.
DDR Mode
DDR mode is not supported — this applies to both MMC version 4.41 and eMMC. Your SDR-only characterization is accurate.
Maximum Clock Speed and Throughput
The MMC Support Matrix confirms eMMC has a maximum clock speed of 50 MHz and a maximum data rate of 50 MB/s. Your theoretical ceiling of 50 MB/s (50 MHz × 8-bit SDR) is consistent with this. The practical read/write figures you cite (40–45 MB/s read, 20–25 MB/s write) are reasonable real-world estimates, though those specific numbers aren't stated in the documentation — label them as empirical observations rather than documented specs.
One correction: HS200 and controller vintage
Your third bullet ("the controller was designed before HS200 existed") is directionally correct but goes beyond what the documentation explicitly states. What the docs do confirm is that the SD/MMC controller is based on the Synopsys DesignWare Mobile Storage Host controller, and the documented maximum is 50 MHz / 50 MB/s SDR. I'd avoid asserting the HS200 non-support as a "controller vintage" argument — just state the documented ceiling directly.
Voltage Switching Note
One thing worth adding for completeness: the SD/MMC controller does not directly support voltage switching, card interrupts, or back-end power control of eSDIO card devices — however, those signals can be connected to GPIOs. This is relevant if your eMMC chip expects 1.8 V signaling for higher-speed modes.
Reset Consideration
Also worth noting for robustness: it is required to reset the QSPI and SD/MMC/eMMC boot flash devices each time there is an HPS reset (warm or cold). The SD/MMC controller does not contain a reset output as part of the external card interface, so consider using a general purpose output pin for this.
Bottom line: your analysis is solid. The 50 MB/s theoretical / ~45 MB/s practical read ceiling is well-supported by the documented specs, and the SDR-only, 50 MHz max characterization is accurate.
Sources: Features of the SD/MMC Controller, SD/MMC Controller, MMC Support Matrix, SD/MMC Controller Block Diagram and System Integration, Cyclone V · HPS/Embedded
