re: Cyclone V 5CSXFC4C6U23C7N LPDDR2 Why an unexpected SDRAM refresh behavior?

BCT Thanks again, it was the DQS tracking feature that surprised us. We don't have a file like *_if0_c0.v but we found *_fmem_s0.v that works. I have two follow-on questions: 1.How can we permanently stop DQS tracking? We can stop it with this before compiling, but the file is overwritten by Qsys/Platform Designer: sth31_fmem_s0.v: sequencer_scc_mgr #( .USE_DQS_TRACKING (1), -> "0" BTW, I've found several other files that reference DQS_TRACKING that are overwritten by Qsys but hacking just them before compiling does not change the fmem dqs tracking behavior: sequencer\emif_pre.xml <sequencer> <define name="USE_DQS_TRACKING" value="1"/> -> "0" <controller> <define name="USE_HPS_DQS_TRACKING" value="true"/> -> false sth31_fmem_p0_altdqdqs.v defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true"; -> "false" sth31_fmem_s0_make_qsys_seq.tcl lappend arg_list "--component-param=USE_DQS_TRACKING=true" -> "false" hps_sdram_p0_altdqdqs.v defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true"; -> "false" [not fmem] 2.Disabling FORCE_DQS_TRACKING in .qsys before generating seems to stop normal refresh, as well as dqs_tracking. is this intended? (if so, the name is deceptive) Thanks in advance, John Den 2019-08-13 kl. 04:52, skrev Intel Forums: