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New Contributor

6 years ago

re: Cyclone V 5CSXFC4C6U23C7N LPDDR2 Why an unexpected SDRAM refresh behavior?

Using 5CSXFC4C6U23C7N CycloneV with 2x MT42L128M32D1LF-25 WT:A LPDDR2 Micron SDRAM: 4Gb (2Mx32b x 8bank) Quartus Prime 18.1 Lite Edition We have noticed a curious feature of the fpga SDRAM: ...

BoonT_Intel

Frequent Contributor

6 years ago

Hi Sir,

The additional wait time might caused by DQS tracking feature of the IP.

See this document for details.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_fd_uniphy.pdf#page=24

Please note that this document also include the step to disable the feature. But use it on your own risk.

Thanks

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re: Cyclone V 5CSXFC4C6U23C7N LPDDR2 Why an unexpected SDRAM refresh behavior?

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