Problem on downloading bitstream to a Stratix 10 MX board

Thanks for your help. I just tried your sof file with the JTAG only mode configuration:

SW2[3:0] = 1111, SW1[3:0] = 1111;

As I showed before, the following picture is my setting of DIP switches:

But again, when pressed the "Auto Detect" button in the Quartus programmer, I got the error message "Unable to scan device chain. Can't scan JTAG chain. Do you want to open the JTAG Chain Debugger to troubleshoot the JTAG chain?"

As I posted before, I suspected that my DIP switch configuration was wrong so that the synchronization between PC and s10mx board cannot be correctly established. Thus, I tried the default DIP switch setting in the following documentation:

https://www.intel.com/content/www/us/en/programmable/documentation/cbc1517362051825.html#sgk1519171036412

Surprisingly, by using that default DIP switch setting, I can successfully download both your sof file (bts_pcie.sof) and my own test sof file (test.sof) to the s10mx board. However, I still have some questions about the unexpected success. But before that, let me first share my configuration of successful downloading the bitstream to the s10 mx board.

(1) Change the DIP switch back to the default setting:

(2) Open the Quartus Programmer, press "Auto Detect" and select the correct JTAG ID for device 1 (1SM21BHU2F53E2VGS1). We should choose "1SM21BHU2S1" for my s10mx board.

(2) Choose the correct JTAG ID for device 2. I think the device 2 means the Intel MAM 10 FPGA Power Manager, so I choose "10M16SA" for my board according to the s10 mx user guide:

https://www.intel.com/content/www/us/en/programmable/documentation/cbc1517362051825.html#sgk1519171036412

(3) Replace the device (1SM21BHU2F53S1) with the bitstream (sof file). And click "Start", the bitstream was successfully downloaded to the board.

However, I'm confused of the following figure from s10mx user guide:

There is a mismatch between the real board and the explanation in terms of the PCIe RT signal. In specific, the PCIe RT setting in the real board was set to the left side. But the PCIe RT setting in the explanation was set to the right side. So my first question is:

(1) What is the corresponding MSEL[2:0] for the real board setting in Figure 3?

Then my second question is:

(2) According to the s10 mx user guide, s10mx supports AS mode (MSEL[2:0] = 001) and JTAG mode (MSEL = 111). I assume the default setting shown in Figure 3 means AS mode and adjust my DIP switches to JTAG mode. But when downloading bitstream in the JTAG mode, I got the error message "Unable to scan device chain. Can't scan JTAG chain. Do you want to open the JTAG Chain Debugger to troubleshoot the JTAG chain?" What is the problem here? I'm not sure what is the correct DIP switch configuration for the JTAG mode (MSEL = 111). A picture of that JTAG configuration will be greatly appreciated.

Thanks,

Hanchen