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GQUIR2's avatar
GQUIR2
Icon for New Contributor rankNew Contributor
6 years ago

Other workflow for generating Preloader since Quartus-Prime Version 19.1 with "SoC EDS 19.1 Command Shell„

I work with FPGA-Eval-Board DE10-Standard from Terasic with Cyclone V and HPS. Before Quartus-Prime Version 19.1 workflow in "SoC EDS 18.1 Command Shell„ was: Generate the "Preloader" using the BSP...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Gerhard,

Have you downloaded and setup the toolchain?

If you have, you will still need to execute the 3 exports which is the export PATH, export CROSS_COMPILE etc.. before executing the make.

Let me know if this does not fix the issue.