Other workflow for generating Preloader since Quartus-Prime Version 19.1 with "SoC EDS 19.1 Command Shell„

I work with FPGA-Eval-Board DE10-Standard from Terasic with Cyclone V and HPS. Before Quartus-Prime Version 19.1 workflow in "SoC EDS 18.1 Command Shell„ was: Generate the "Preloader" using the BSP...