Is it possible to reach nearby CLBs optimally fast while using openCL?

Hi,

If I understand you correctly, you are trying to read directly from CLB.

Let me explain how logic is implemented in FPGA.

In FPGA user logic written in (HDL language like verilog/ VHDL) or even OpenCL kernel code get implemented in CLB by Quartus. Having said that Quartus will go through Synthesis followed by Fitter stage to populate logic in CLB's. So its a netlist that is implemented in CLB's, Fitter optimizes the location to achieve performance.

I don't think you will be able to read from CLB it self, best you can do is open Chip Planner and see how logic is implemented.

Hope this helps.

Thanks,

Arslan