Intel® Stratix® 10 L- and H-Tile Transceiver PHYの使い方について

Hi

The following is the description in English.

Q1. It is a question about the power-on sequence of PCIe Phy in Stratix10.

According to the user manual, I think that to assert signal "rx_is_lockedtodata", it's necessary to receive some toggled signal from link partner by rx_serial_data. Otherwise, the reset would not end and signal "phystatus" would not be de-asserted. Is my understanding correct?

Q2. It is an additional question in case that answer to Q1 is yes.

To finish the reset of PCIe phy, the Phy in Host-side must finish its reset before Local-side does, otherwise the Host-side can not transmit toggled signal to Local side. In case that I connect 2 stratix10 PCIe phys as Local and Host, I think I should consider a method to transmit data to each other within their reset period. Is that correct?

P.S. In my simulation, if I don't do this, signal "rx_is_lockedtodata" can not be asserted and "rx_digitalreset" never end as both side can not receive toggled signal from their link-partner.

Best regards